1. Field of the Invention
This invention relates to clock circuits of the type employed to synchronize operations in a mainframe computer. More particularly, the present invention relates to multiple clock circuits for multiple mainframe computers that are synchronized together so that they are capable of communicating with each other in real time.
2. Description of the Prior Art
It is well known that central processing units (CPU's) have been connected in clusters and operated in a distributed processing manner so that they require master clocks. Heretofore, one of the master clocks of a plurality of CPU's in a cluster configuration has been employed as the master clock for synchronizing other computers in the cluster. However, problems have arisen with delays of the clock pulses in the signal lines leading to the other computers and when a single clock is employed high power drivers are required to drive the clock signal load.
It has been suggested that individual clock circuits with individual drivers be supplied at each of the computers in a cluster configuration and that the clock circuits at the individual CPU's be synchronized by a master oscillator so that the aforementioned problems with the delay of the clock signals in signal lines and high power driver requirements can easily be overcome at the individual computers.
Another problem arises at the individual clock boards at the individual computers. The duration of the phases of the clock is theoretically precise and accurate, however, it has been found that the prior art method of employing cascaded flip-flops to generate different phases of the clock signal do not generate accurate time period windows for the clock phases. For example, an 80 nanosecond clock having four phases would require that the duration of each phase last exactly 20 nanoseconds without overlap or separation. Due to process variation in manufacturing the semiconductors used for the flip-flops, voltage variations at the semiconductors and temperature variations of the environment, the 20 nanosecond windows have been found to vary in excess of 10% when an acceptable variation of less than 2% is required in a high speed computing system to prevent system malfunction. Computer manufacturers, more than five years ago, did not incur this problem because the clock rates were relatively low. Today's high speed computers require that the logic and clock circuits be embodied in the form of large scale or very large scale integrated circuits, thus, when a clock circuit that is otherwise operable but is not acceptable because of pulse durations or frequency durations of the clock (or the phases of the clock), the whole semiconductor device having the clock circuits is not acceptable. Further, if the semiconductor device on which the clock circuit is located is embodied into a component, subcomponent or board and the unacceptable time variations of the clock (or phases of the clock) are not discovered until after assembly, the whole assembly must be either reworked or scrapped.
It would be extremely desirable to provide a simplified clock circuit which may be incorporated into a semiconductor chip with other logic circuits which is not subject to time duration variations caused by variations in temperature environment or voltage supply.